AM4 Timings
Reference profile for DDR4-3600 on AMD AM4. Names match common UEFI / ZenTimings labels; your board may use tRRD_L / tRRD_S instead of tRRD_sg / tRRD_dg, and tRDRDscl / tRDRDsc instead of RDRD_sg / RDRD_dg.
Validate before daily use
Run stability testing (TM5, Karhu, or Y-Cruncher) after applying these values. Timings that look fine in BIOS can still fail under load.
Profile summary
| Setting | Value |
|---|---|
| Data rate | 3600 MT/s (DDR4-3600) |
| Primary (CAS label) | 14-14-14-28 |
| Command rate (CR) | 1T |
Approximate latency (read): ~7.8 ns CAS 2000 × 14 / 3600 ≈ 7.78 ns (same formula as DDR4 docs).
Primary timings
| Timing | Value | Role |
|---|---|---|
| tCL | 14 | READ command → first data on DQ |
| tRCD | 14 | ACT → READ/WRITE |
| tRP | 14 | PRE → idle (same bank) |
| tRAS | 28 | ACT → PRE (row open time) |
| CR | 1 | Command rate (1T) |
tRC (often hidden in BIOS)
On AM4, tRC is usually derived. A safe starting point is tRP + tRAS → 14 + 28 = 42. If the board exposes tRC, set it to 42 or leave Auto if stable.
Sub-timings
| This guide | Common BIOS / ZenTimings | Value | Notes |
|---|---|---|---|
| tRTP | tRTP | 8 | READ → PRE (same bank) |
| tRRD_sg | tRRD_L, tRRDL | 4 | ACT → ACT, same bank group |
| tRRD_dg | tRRD_S, tRRDS | 4 | ACT → ACT, different bank group |
| tFAW | tFAW | 16 | Gap before a 5th ACT in a window (4 × tRRD_dg) |
| RDRD_sg | tRDRDscl, RDRD_SCL | 7 | READ → READ, same group |
| RDRD_dg | tRDRDsc, RDRD_SC | 4 | READ → READ, different group |
What each group affects (FPS / bandwidth)
| Area | Timings | Tightening tends to… |
|---|---|---|
| Latency | tCL, tRCD, tRP, tRAS | Lower = snappier RAM response; needs voltage headroom |
| Row changes | tRTP, tRRD_*, tFAW | Helps bandwidth in mixed workloads; too tight → TM5 errors |
| Read bandwidth | RDRD_sg, RDRD_dg | Noticeable in AIDA64 / some games; RDRD_dg = 4 is fairly tight on AM4 |
| Command rate | CR 1T | Lower latency than 2T; can be less stable above DDR4-3600 |
Community notes for AM4 DDR4-3600 (see also Intel DDR4 guide AMD IMC):
- Gear Down Mode (GDM) is often forced on above DDR4-2666 even tCL/tRTP and CR 1T.
- Keep MCLK : FCLK 1:1 on Zen2/Zen3 AM4 for best latency (do not rely on desync for “free” MT/s).
- SOC / CLDO_VDDP may need a small bump when pushing RDRD or tRRD below JEDEC defaults.
Suggested voltages (starting point)
| Voltage | Typical range @ DDR4-3600 |
|---|---|
| DRAM voltage (VDIMM) | 1.35–1.45 V (kit-dependent) |
| SOC | 1.05–1.15 V (IMC-dependent) |
Do not copy someone else’s SOC/VDIMM validate on your CPU and IC (Micron, Samsung, Hynix bins differ).
Samsung DDR4 8Gb B-die timing guidelines for Ryzen
Aug 10, 2022
Viable for 3600–4000 MT/s but skewed towards 3800 MT/s with 1.4–1.65 V depending on RAM chip quality. With GDM enabled.
Note that most Ryzen 3000/5000 CPUs will not do more than 1900 FCLK stable.
Also keep in mind that B-die is the least consistent DDR4 IC that I'm aware of. Unbinned/OEM B-die and low XMP spec B-die like 3200 16-18… can often struggle to scale to even 1.45 V while being extremely temperature sensitive and doing horrific tCL, tRCDRD and tRP like 3600 18-18-18 at 1.4 V levels of horrific. On the flip side it is still B-die and so subtimings like tRFC can still go low.
Primary timings
| Timing | Range | Notes |
|---|---|---|
| tCL | 14–18 | Can't be odd with GDM turned on |
| tRCDWR | 8–18 | 8 works most of the time; doesn't affect performance much |
| tRCDRD | 13–18 | Most good kits max out at 15 |
| tRP | 11–18 | Low tRP is more important than low tRAS |
| tRAS | 24–32 | Set so that tRAS + tRP = tRC |
| tRC | 38–50 | Around 40 should work as long as your RAM doesn't suck |
Sub-timings
| Timing | Range | Notes |
|---|---|---|
| tRRD_S | 4 | Always does 4 |
| tRRD_L | 4–6 | Weaker DIMMs might need 6 to be stable |
| tFAW | 16 | Always works |
| tWTR_S | 3–5 | 4 works most of the time; with a lot of voltage some sticks can do 3 |
| tWTR_L | 7–10 | 8 works most of the time; with a lot of voltage some sticks can do 7 |
| tWR | 10–12 | I'd be very surprised if 10 doesn't work for you |
| tRFC | 220–330 | Usually just use 280 |
| tCWL | tCL or tCL−2 | No point pushing lower raises RDWR and WRRD if you do |
| tRTP | 6–12 | 8 works on most good kits |
| tRDRDSCL | 2–4 | 2 works most of the time |
| tWRWRSCL | 2–4 | 2 works most of the time |
| tRDWR | Auto | Leave on auto |
| tWRRD | Auto | Leave on auto too |
| tRDRDSC | 1 | Auto = 1 |
| tRDRDSD | 4 | Only applies to multi-rank setups |
| tRDRDDD | 4 | Only applies to multi-rank setups |
| tWRWRSC | 1 | — |
| tWRWRSD | 6 | Only applies to multi-rank setups |
| tWRWRDD | 6 | Only applies to multi-rank setups |
| tCKE | 1 | Always works |
Lazy preset (3200 14-14 or better XMP)
If you're very lazy and your kit has a 3200 14-14 or better XMP, the following settings should work. They aren't gonna be much slower than some hyper optimized 3800 C14 settings.
Clocks & voltage
| Setting | Value |
|---|---|
| FCLK | 1866 |
| MCLK | 3733 |
| VDIMM | 1.45 V (recommend a fan pointed at the RAM) |
| VSOC | 1.1 V |
| GDM | Enabled |
Primary timings
| Timing | Value |
|---|---|
| tCL | 16 |
| tRCDWR | 16 |
| tRCDRD | 16 |
| tRP | 16 |
| tRAS | 28 |
| tRC | 44 |
Sub-timings
| Timing | Value |
|---|---|
| tRRD_S | 4 |
| tRRD_L | 6 |
| tFAW | 16 |
| tWTR_S | 4 |
| tWTR_L | 8 |
| tWR | 10 |
| tRFC | 300 |
| tRDRDSCL | 2 |
| tWRWRSCL | 2 |
| tCWL | 16 |
| tRTP | 8 |
| tRDWR | Auto |
| tWRRD | Auto |
| tRDRDSC | 1 |
| tRDRDSD | 4 |
| tRDRDDD | 4 |
| tWRWRSC | 1 |
| tWRWRSD | 6 |
| tWRWRDD | 6 |
| tCKE | 1 |
This last set of timings is pretty much what a B-die "XMP" should/could look like if XMP was able to hold all the settings.
Related
- Memory stability testing
- Intel DDR4 timings shared DDR4 concepts, IC tables, AMD IMC section
- Safe fallback timings looser profile if this kit fails training