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AM5 - Hynix M-die Timings ​

Reference for Ryzen AM5 with Hynix M-die 16 GB modules PDF exports below, plus a folded text copy of the preset tables and glossary.

PDF reference ​

Version 0.2 ​

R5-D5-H16M · AM5 · Hynix M-die (16 Gb) · v0.2

PDFDDR5 timing presets · v0.2
am5-hynix-m-die-ddr5-timing-presets-v0.2.pdf
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Version 0.1 ​

Ryzen AM5 · Hynix M-die (16 Gb) · v0.1 (older revision)

PDFDDR5 timing presets · v0.1
am5-hynix-m-die-ddr5-timing-presets-v0.1.pdf
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Text quick reference ​

Same data as the sheets above, collapsed by default open a block to copy values. XMP/EXPO means use the kit’s profile for that cell.

DDR5-6000 · fallback / “easy” / BZ lazy
SettingFallbackEasyBZ lazy
UCLK : MCLK1:11:11:1
MCLK300030003000
UCLK300030003000
FCLK200020002133
VSOC1.251.251.25
DRAM VDD1.35auto1.43
DRAM VDDQautoautoauto
VDDIOautoautoauto
VDDP0.950.950.95
tCL32XMP/EXPO30
tRCDWR38XMP/EXPO16
tRCDRD38XMP/EXPO36
tRP38XMP/EXPO36
tRAS126126126
tRC606060
tWR484848
tRFC512512512
tRFC2not usednot usednot used
tRFCSBnot usednot usednot used
tREFI400005000065535
tRTP161616
tRRDL888
tRRDS884
tFAW323220
tWTRL161616
tWTRS644
tRDRDSCL444
tRDRDSC111
tRDRDSD666
tRDRDDD666
tWRWRSCL422
tWRWRSC111
tWRWRSD888
tWRWRDD888
tWRRD444
tRDWR161616
Nitro RX Dataautoauto1
Nitro TX Dataautoauto2
Nitro Control Lineautoauto0
  • tRCDWR: if the board has no tRCDWR, use tRCDRD only.
  • tRDRDSD / tRDRDDD / tWRWRSD / tWRWRDD: multi-rank setups only.
  • tREFI 65535: RAM fan recommended.
DDR5-6200 · fallback / “easy” / BZ lazy

UMC lottery (Ryzen 9000)

On some CPUs the UMC will not run 3100 MHz (1:1) even with ~1.3 V VSOC, so DDR5-6200 1:1 may be impossible. Prefer 1:1 @ 6000 or 2:1 @ 7600+ if that happens.

SettingFallbackEasyBZ lazy
UCLK : MCLK1:11:11:1
MCLK310031003100
UCLK310031003100
FCLK206620662066
VSOC1.31.31.3
DRAM VDD1.35auto1.43
DRAM VDDQautoautoauto
VDDIOautoautoauto
VDDP0.950.950.95
tCL34XMP/EXPO32
tRCDWR40XMP/EXPO16
tRCDRD40XMP/EXPO37
tRP40XMP/EXPO37
tRAS126126126
tRC626262
tWR484848
tRFC544512512
tRFC2not usednot usednot used
tRFCSBnot usednot usednot used
tREFI400005000065535
tRTP161616
tRRDL888
tRRDS884
tFAW323220
tWTRL161616
tWTRS644
tRDRDSCL644
tRDRDSC111
tRDRDSD666
tRDRDDD666
tWRWRSCL622
tWRWRSC111
tWRWRSD888
tWRWRDD888
tWRRD644
tRDWR181616
Nitro RX Dataauto11
Nitro TX Dataauto32
Nitro Control Lineauto10
  • tRCDWR: if the board has no tRCDWR, use tRCDRD only.
  • FCLK: if stable, 2166 or 2200 can be a bit faster than 2066.
  • Multi-rank-only timings and tREFI 65535 fan note same as DDR5-6000 block.
DDR5-6400 · fallback / “easy” / BZ lazy

UMC ceiling (Ryzen 9000)

Many Ryzen 9000 CPUs will not do 3200 MHz UCLK/MCLK (1:1) even at ~1.3 V VSOC, so DDR5-6400 1:1 may be impossible. Prefer 1:1 @ 6200 or 2:1 @ 7600+.

SettingFallbackEasyBZ lazy
UCLK : MCLK1:11:11:1
MCLK320032003200
UCLK320032003200
FCLK210021332133
VSOC1.31.31.3
DRAM VDD1.35auto1.43
DRAM VDDQautoautoauto
VDDIOautoautoauto
VDDP0.950.950.95
tCL34XMP/EXPO32
tRCDWR40XMP/EXPO16
tRCDRD40XMP/EXPO38
tRP40XMP/EXPO38
tRAS126126126
tRC646464
tWR484848
tRFC544544544
tRFC2not usednot usednot used
tRFCSBnot usednot usednot used
tREFI400005000065535
tRTP161616
tRRDL1088
tRRDS884
tFAW323220
tWTRL161616
tWTRS644
tRDRDSCL664
tRDRDSC111
tRDRDSD666
tRDRDDD666
tWRWRSCL622
tWRWRSC111
tWRWRSD888
tWRWRDD888
tWRRD644
tRDWR181616
Nitro RX Dataautoauto1
Nitro TX Dataautoauto3
Nitro Control Lineautoauto1
  • tRCDWR: if the board has no tRCDWR, use tRCDRD only.
  • Multi-rank-only timings and tREFI 65535 fan note same as above.
Profiles · what “fallback / easy / BZ lazy” mean
  • fallback Starting point mainly for kits that struggle with tighter presets.
  • “easy” Expected to work in almost all typical setups.
  • BZ lazy Daily-driver style profile the author would try first.
Glossary · clocks & voltage

Ratio

  • Ratio of DRAM + PHY clock to memory controller clock (UCLK : MCLK).

UCLK

  • Memory controller clock trades latency vs bandwidth.

MCLK

  • DRAM + PHY clock trades latency vs bandwidth.

FCLK

  • Infinity Fabric clock latency vs bandwidth.

VSOC

  • SoC voltage (about 0.9–1.3 V typical ceiling guidance in sheet context); strongly influences max UCLK. In 2:1, lower UCLK can allow very low VSOC.

DRAM VDD

  • DRAM “core” voltage (about 1.35–1.75 V range mentioned); high VDD (~1.5 V+) often aimed at tight tCL (e.g. 8000 C34 / 6400 C26). Beyond ~1.65 V can hurt stability.

DRAM VDDQ

  • DRAM I/O voltage signaling RAM ↔ CPU (about 1.1–1.65 V); avoid going over ~1.65 V. Sweet spot varies by board, RAM, BIOS often ~1.25–1.45 V.

VDDIO

  • PHY I/O voltage signaling CPU ↔ RAM (about 1.1–1.5 V, ~1.5 V max cited). Typical tuning band ~1.25–1.5 V, board/RAM dependent.

VDDP

  • PHY voltage (about 0.95–1.15 V, ~1.15 V max). Too low or too high loses stability.
Glossary · timing parameters

tCL

  • READ → first data burst; lowers read/write latency.

tRCDWR

  • ACT → WRITE; row open delay before WRITE lowers write latency; can be very short because writes overwrite the row.

tRCDRD

  • ACT → READ; row open delay before READ lowers read latency.

tRP

  • PRE → ACT same bank how soon another row opens in the bank (faster row changes).

tRAS

  • ACT → PRE same bank how soon you close after opening (mostly matters when the MC opens then immediately closes).

tRC

  • ACT → ACT same bank how fast you switch active rows (same “immediate hop” caveat).

tWR

  • WRITE → PRE same bank how soon you close after WRITE.

tRFC

  • Refresh duration idle window after REF before other commands; higher tRFC / tREFI fraction means more cycles “lost” to refresh.

tRFC2 / tRFCSB

  • Unused in these presets.

tREFI

  • Interval between REF commands higher tREFI frees more bandwidth but needs colder DRAM (often < ~55 °C for very high values like 65535).

tRTP

  • READ → PRE how soon you close after READ.

tRRDL

  • ACT → ACT same bank group going below 8 usually does little because DDR5 burst is 8 cycles.

tRRDS

  • ACT → ACT different bank group same note about < 8.

tFAW

  • Four-ACT window backs off a 5th ACT if four ACTs happened too fast.

tWTRL / tWTRS

  • WRITE → READ (same BG vs different BG) bandwidth vs turnaround.

tRDRDSCL / tRDRDSC

  • READ → READ (same BG vs different BG) bandwidth; tRDRDSC > 1 hurts bandwidth badly.

tRDRDSD / tRDRDDD

  • READ → READ across ranks (same DIMM vs different DIMMs) bandwidth.

tWRWRSCL / tWRWRSC

  • WRITE → WRITE (same BG vs different BG) bandwidth; tWRWRSC > 1 hurts badly.

tWRWRSD / tWRWRDD

  • WRITE → WRITE across ranks (same DIMM vs different DIMMs) bandwidth.

tWRRD

  • WRITE → READ across ranks bandwidth.

tRDWR

  • READ → WRITE (general turnaround).

Work in progress

Cross-check against your motherboard BIOS naming and the PDF revisions above before flashing tunings “blind”.